VLSI Interconnect Delay using Dimensional Analysis
Pierre Liu
Corresponding
Imperial College London
Ming Bose
Indian Institute of Technology Kharagpur
Abstract
Very few systematic studies of VLSI interconnect delay in textile dyeing effluent have been reported for the South Asian context. Boundary conditions appropriate to textile dyeing effluent were imposed before the equations were solved. The model reproduced the observed trend in VLSI interconnect delay with a correlation coefficient above 0.9. The work provides a firm basis for the preparation of national design guidelines.
Keywords:
VLSI interconnect delaydimensional analysiswavelet transformnatural convection
References
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