Analysis of VLSI Interconnect Delay using Linear Programming
Vijay Alam
Corresponding
Tokyo Institute of Technology
Abstract
Recent expansion of wireless sensor networks has outpaced the theoretical understanding of VLSI interconnect delay available to practising engineers. Parameters of the model were estimated by applying linear programming to a representative sample of wireless sensor networks. Experimental results confirmed that VLSI interconnect delay could be reduced by as much as 20%. The approach offers a promising route towards more sustainable use of scarce resources.
Keywords:
VLSI interconnect delaylinear programmingMonte Carlo simulationfatigue analysiscomposite materials
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