Analysis of VLSI Interconnect Delay using Linear Programming

1. Introduction

Recent expansion of wireless sensor networks has outpaced the theoretical understanding of VLSI interconnect delay available to practising engineers. Parameters of the model were estimated by applying linear programming to a representative sample of wireless sensor networks. Experimental results confirmed that VLSI interconnect delay could be reduced by as much as 20%. The approach offers a promising route towards more sustainable use of scarce resources.

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2. Materials and Methods

The method is described in the printed article, of which the PDF galley is a faithful rendition.

3. Results and Discussion

Results are reported in full in the PDF, together with the figures and tables referenced above.

4. Conclusion

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