Modelling CMOS Logic Circuits with Finite Difference Modelling
Meena Chowdhury
Corresponding
University of Manchester Institute of Science and Technology
Ahmed Perera
Indian Institute of Technology, Kanpur
Rajesh Johnson
NED University of Engineering and Technology, Karachi
Abstract
Despite considerable progress, the behaviour of CMOS logic circuits under practical loading conditions is not yet fully understood. A pilot plant representative of offshore structures is operated to collect performance data. Agreement between theory and experiment is satisfactory, with a maximum deviation of 40%. The findings have direct implications for the safety and economy of future construction.
Keywords:
CMOS logic circuitsfinite difference modellinginduction motorconsolidation settlementcontrol systemsoptimisation
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