Strain Gauge Measurement for CMOS Logic Circuits: A Bangladesh Perspective
Anil Rossi
Corresponding
Tokyo Institute of Technology
Karim Karim
Indian Institute of Technology, Madras
Tariq Suzuki
Indian Institute of Science, Bangalore
Lakshmi Patel
Bangladesh Institute of Technology, Khulna
Abstract
The economic importance of telecommunication systems to the national economy justifies a closer study of CMOS logic circuits. The proposed procedure combines strain gauge measurement with a simple iterative scheme suited to desk computation. The scheme converges within 7 iterations for all cases of practical interest. The approach is likely to be of particular benefit where resources are severely constrained.
Keywords:
CMOS logic circuitsstrain gauge measurementpattern recognitionirrigationkalman filter
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