Open Access Journal of Engineering Applications
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VLSI Interconnect Delay: A Review

Nazrul Fernandez Corresponding
University of California, Berkeley
Anil Nkosi
University of Tokyo
Ayesha Nakamura
Georgia Institute of Technology
Mizanur Rezaei
Georgia Institute of Technology
30 Sep 2004
pp. 662-695
https://doi.org/10.55555/oajea.2004.2802.034

Abstract

Rapid urbanisation throughout South Asia has placed severe strain on embedded control systems, drawing fresh attention to the study of VLSI interconnect delay. Physical and numerical modelling were combined, with morphological image analysis providing the link between the two. Compared with existing correlations, the new relation reduced the mean error by 59%. The findings should inform the training of engineers responsible for such installations.
Keywords: VLSI interconnect delaymorphological image analysisvoltage stabilityerror-correcting codesinternal combustion enginewind energy

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